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skill
hdl-fault-localization
ANo problem foundAgainstWar/HDL-Repair-Skills
Use this skill to systematically localize bugs in HDL/RTL designs (Verilog, SystemVerilog, VHDL) by generating multiple evidence-backed root-cause hypotheses. Trigger whenever the user reports simulation failures, testbench mismatches, synthesis/simulation mismatches, unexpected signal values, protocol violations (AXI/AHB/APB), state machine misbehavior, formal verification failures, or any RTL bug symptoms — including "my testbench fails", "signal X is stuck", "assertion fires", "why is this m…
hdl-fault-localization got grade A on our automated scan on 2026-10-21.
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